The Taiwan Semiconductor Manufacturing Company (TSMC) has silently introduced new performance-enhanced versions of its 7nm DUV (N7) and 5nm EUV (N5) manufacturing processes, called N7P and N5P, respectively.
TSMC’s 7NP performance-enhanced process, which is DUV-based, is not to be confused with the company’s N7+, which is TSMC’s first process to use extreme ultraviolet lithography (EUV). The N7P is simply an optimization of N7 process; it uses the same design rules and is fully IP compatible with N7.
This is why many of TSMC’s customers are expected to stick to N7P over switching to N7+. These customers prefer jumping straight to the 5nm EUV or the 6nm EUV (EUV equivalent of N7 with more EUV layers) processes later on instead of using TSMC’s first-generation 7nm EUV process. The optimizations brought to the N7P process are expected to allow TSMC customers to increase their chips’ performance by 7% or decrease power consumption by 10%.
Meanwhile, the N7+ process is expected to deliver a 20% increase in density, a 10% increase in performance, or alternatively a 15% power decrease. Although these improvements are slightly larger than what N7P offers, they also come with the cost of a new physical re-implementation and new EUV masks. The N7P process has already entered mass production in the last quarter (Q2 2019).
As with the N7P, TSMC plans to offer a performance-optimized version of N5, its next-generation “full node,” which is expected to be used by most of TSMC’s customers in the near future once they switch from the 7nm processes. The process uses the same design rules and if is fully IP compatible with the N5 EUV process.
The N5 process promises 80% density improvement over N7, and either 15%-25% higher performance or 30% lower power compared to N7. N5 is expected to be long-lived and server both mobile and high-performance computing (HPC) customers.
The N5P promises to either increase the performance by 7% or decrease power consumption by 15% compared to N5. The N5P is expected to arrive by early 2021.