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Data I/O Bus, Address Bus, And Internal Registers

Upgrading And Repairing PCs 21st Edition: Processor Specifications
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Data I/O Bus

Two of the more important features of a processor are the speed and width of its external data bus. These define the rate at which data can be moved into or out of the processor.

Data in a computer is sent as digital information in which certain voltages or voltage transitions occurring within specific time intervals represent data as 1s and 0s. You can increase the amount of data being sent (called bandwidth) by increasing either the cycling time or the number of bits being sent at a time, or both. Over the years, processor data buses have gone from 8 bits wide to 64 bits wide. The more wires you have, the more individual bits you can send in the same interval. All mod- ern processors from the original Pentium and Athlon through the latest Core i7, AMD FX 83xx series, and even the Itanium series have a 64-bit (8-byte)-wide data bus. Therefore, they can transfer 64 bits of data at a time to and from the motherboard chipset or system memory.

A good way to understand this flow of information is to consider a highway and the traffic it carries. If a highway has only one lane for each direction of travel, only one car at a time can move in a cer- tain direction. If you want to increase the traffic flow (move more cars in a given time), you can either increase the speed of the cars (shortening the interval between them), add more lanes, or both.

As processors evolved, more lanes were added, up to a point. You can think of an 8-bit chip as being a single-lane highway because 1 byte flows through at a time. (1 byte equals 8 individual bits.) The 16-bit chip, with 2 bytes flowing at a time, resembles a two-lane highway. You might have four lanes in each direction to move a large number of automobiles; this structure corresponds to a 32-bit data bus, which has the capability to move 4 bytes of information at a time. Taking this further, a 64-bit data bus is like having an eight-lane highway moving data in and out of the chip.

After 64-bit-wide buses were reached, chip designers found that they couldn’t increase speed further, because it was too hard to synchronize all 64 bits. It was discovered that by going back to fewer lanes, it was possible to increase the speed of the bits (that is, shorten the cycle time) such that even greater bandwidths were possible. Because of this, many newer processors have only 4-bit or 16-bit-wide data buses, yet they have higher bandwidths than the 64-bit buses they replaced.

Another improvement in newer processors is the use of multiple separate buses for different tasks. Traditional processor design had all the data going through a single bus, whereas newer processors have separate physical buses for data to and from the chipset, memory, and graphics card slot(s).

Address Bus

The address bus is the set of wires that carry the addressing information used to describe the memory location to which the data is being sent or from which the data is being retrieved. As with the data bus, each wire in an address bus carries a single bit of information. This single bit is a single digit in the address. The more wires (digits) used in calculating these addresses, the greater the total number of address locations. The size (or width) of the address bus indicates the maximum amount of RAM a chip can address.

The highway analogy in the previous section, “Data I/O Bus,” can show how the address bus fits in. If the data bus is the highway and the size of the data bus is equivalent to the number of lanes, the address bus relates to the house number or street address. The size of the address bus is equivalent to the number of digits in the house address number. For example, if you live on a street in which the address is limited to a two-digit (base 10) number, no more than 100 distinct addresses (00–99) can exist for that street (102). Add another digit, and the number of available addresses increases to 1,000 (000–999), or 103.

Computers use the binary (base 2) numbering system, so a two-digit number provides only four unique addresses (00, 01, 10, and 11), calculated as 22. A three-digit number provides only eight addresses (000–111), which is 23. For example, the 8086 and 8088 processors use a 20-bit address bus that calculates a maximum of 220, or 1,048,576 bytes (1MB), of address locations. The following table describes the memory-addressing capabilities of processors.

64-bit AMD/Intel
Address Bus
40-bit
Bytes
1,099,511,627,776
KiB
1,073,741,824
MiB
1,048,576
GiB
1024
TiB
1

The data bus and address bus are independent, and chip designers can use whatever size they want for each. Usually, however, chips with larger data buses have larger address buses. The sizes of the buses can provide important information about a chip’s relative power, measured in two important ways. The size of the data bus indicates the chip’s information-moving capability, and the size of the address bus tells you how much memory the chip can handle.

Internal Registers (Internal Data Bus)

The size of the internal registers indicates how much information the processor can operate on at one time and how it moves data around internally within the chip. This is sometimes also referred to as the internal data bus. A register is a holding cell within the processor; for example, the processor can add numbers in two different registers, storing the result in a third register. The register size determines the size of data on which the processor can operate. The register size also describes the type of software or commands and instructions a chip can run. That is, processors with 32-bit internal registers can run 32-bit instructions that are processing 32-bit chunks of data, but processors with 16-bit registers can’t. Processors from the 386 to the Pentium 4 use 32-bit internal registers and can run essentially the same 32-bit OSs and software. The Core 2, Athlon 64, and newer processors have both 32-bit and 64-bit internal registers, which can run existing 32-bit OSs and applications as well as newer 64-bit versions.

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Top Comments
  • 11 Hide
    DelightfulDucklings , October 14, 2013 10:22 PM
    Very interesting article, I quite enjoyed the part about Cache memory
Other Comments
  • 5 Hide
    xkm1948 , October 14, 2013 9:13 PM
    Really nice intro article!
  • 11 Hide
    DelightfulDucklings , October 14, 2013 10:22 PM
    Very interesting article, I quite enjoyed the part about Cache memory
  • 2 Hide
    kindiana , October 14, 2013 10:27 PM
    nice article
  • 9 Hide
    burnley14 , October 14, 2013 10:29 PM
    One of the most interesting and informative articles I've ever read on the site. Great job!
  • 2 Hide
    aredflyingbird , October 14, 2013 10:41 PM
    Agreed, excellent article.
  • 2 Hide
    palladin9479 , October 14, 2013 10:55 PM
    Really good article, actually was spot on with how caching works.
  • 3 Hide
    AndrewJacksonZA , October 15, 2013 12:22 AM
    "Forward From The Editor"
    Shouldn't that be "Foreword?"
  • 3 Hide
    iam2thecrowe , October 15, 2013 2:23 AM
    I need more cache in my kitchen.
  • 0 Hide
    LalitMotagi , October 15, 2013 2:25 AM
    Great Article.
  • -1 Hide
    Rex Romero , October 15, 2013 2:30 AM
    Andrew. It's so advanced so it's forward. lol
  • 1 Hide
    groundrat , October 15, 2013 4:04 AM
    Excellent article.
  • 0 Hide
    ojas , October 15, 2013 5:22 AM
    Quote:
    For example, if you live on a street in which the address is limited to a two-digit (base 10) number, no more than 100 distinct addresses (00–99) can exist for that street (102). Add another digit, and the number of available addresses increases to 1,000 (000–999), or 103.

    Should be 10^2, 10^3, and in the next para, 2^x.
  • 0 Hide
    ojas , October 15, 2013 6:11 AM
    Quote:
    Note: Early versions of EM64T-equipped processors from Intel lacked support for the LAHF and SAHF instructions used in the AMD64 instruction set.

    This was very interesting, considering both instructions were supported even by the humble 8086.
  • 3 Hide
    spookyman , October 15, 2013 6:20 AM
    I have one still from 18 years ago. Still one of the best tech books I own. Though mine was just starting to touch the Intel Pentium processor. It even covered IBM's PS/2 computers and technology. Its amazing how much more hardware intensive PC's were back then they are now.
  • 0 Hide
    ojas , October 15, 2013 6:50 AM
    I ended up buying the 19th edition after last year's excerpts on Tom's Hardware, the 20th wasn't available in India then.

    These sections seem more or less unchanged, except for the mention of Ivy and Vishera, and i think the CPU-z screenshots are new as well.
  • 0 Hide
    AndrewJacksonZA , October 15, 2013 6:54 AM
    Quote:
    Quote:
    Note: Early versions of EM64T-equipped processors from Intel lacked support for the LAHF and SAHF instructions used in the AMD64 instruction set.

    This was very interesting, considering both instructions were supported even by the humble 8086.
    Apparently they were missing from the early 64bit CPUs from AMD and Intel. They appeared in March 2005 for AMD CPUs and June 2005 for Intel CPUs
    https://en.wikipedia.org/wiki/X86-64#Older_implementations

    Yet at the very least the 80386 supported them:
    http://css.csail.mit.edu/6.858/2011/readings/i386/LAHF.htm

    So it appears that it was an early-64 bit CPU issue only.
  • 0 Hide
    ta152h , October 15, 2013 9:04 AM
    I could only get to page three before being thoroughly disgusted by the lack of knowledge of the writer. How can he be writing books, without actually knowing the material?

    The Prescott introduced 64-bit to the Intel world, not the Core 2. Kind of common knowledge. The Athlon XP had a 36-bit address bus? I don't remember ever seeing that.

    Then we go to the misinformation about the 8086/8088 to 386.

    In actuality, there were four modes in the 80386. Real, Virtual 86, Protected 286, and Protected 386. Yup, four. And no, Windows 3.0 was not expected to run on an 8088 or 80286, because it DID use Virtual 86, which those processors could not support. You know, the part where they let you go from one DOS task to another. That was in the hardware. And that hardware started with the 80386.

    Moreover, the 80286 did NOT have the same instruction set as the 8086. Only in real mode did it. And why do you suppose it was called real mode? Maybe because the addresses were not virtualized? The 80286, as mentioned above, did have virtual addresses in what was called the 80286 Protected Mode. It not only ran Real Mode apps much faster, but when in Protected Mode was very capable of running multitasking Operating Systems, something that could not be done well on the 8086. It also increased the memory bus to 24-bits, albeit still using 64K bit segments.

    OS/2 1.x was the best example of an OS using 286 Protected mode, although any software using "Extended Memory" was taking advantage of the greater addressing of the 286, albeit in an inelegant way.

    I stopped reading after page three, as it's just discouraging to think people are writing books without being accurate. OK, so we have the author that got it wrong, fair enough, but what about the people who are supposed to error check it. I certainly don't know everything, and I know this stuff, and it's pretty basic. No one caught this? Are you kidding me? The 286 stuff might be a bit far away, but not knowing that x86-64 first appeared in the Prescott line is really difficult to understand, and is very basic. This is made more so because of all the rumors that the processor was made to support it, but Intel was hiding it so as to not undercut the Itanium. In time, it was proven true.

    Please, don't spread misinformation. Someone will repeat this stuff, and then someone else will, and it becomes 'fact' despite being wrong. If you publish a book, make a friggin effort! I'm sure I could errors the rest of the way, but it's just too annoying for me to wade through this rubbish.

    By the way, the term CPU bus is an ambiguous one. The CPU has multiple buses, and if you used that term with me, I'd wonder which one you were referring to. Find a more accurate term, like PCI-E bus if that's what you are trying to say.
  • -2 Hide
    ezorb , October 15, 2013 9:22 AM
    I feel that this is bellow the level of this website, even below the level of Maximum PC (which has a great podcast), this is the book my grandfather would buy if he wanted to try his hand at build a PC
  • -1 Hide
    hardrock40 , October 15, 2013 10:08 AM
    Really nice article well worth the read for sure.
  • -2 Hide
    ta152h , October 15, 2013 10:42 AM
    I could only get to page three before being thoroughly disgusted by the lack of knowledge of the writer. How can he be writing books, without actually knowing the material?

    The Prescott introduced 64-bit to the Intel world, not the Core 2. Kind of common knowledge. The Athlon XP had a 36-bit address bus? I don't remember ever seeing that.

    Then we go to the misinformation about the 8086/8088 to 386.

    In actuality, there were four modes in the 80386. Real, Virtual 86, Protected 286, and Protected 386. Yup, four. And no, Windows 3.0 was not expected to run on an 8088 or 80286, because it DID use Virtual 86, which those processors could not support. You know, the part where they let you go from one DOS task to another. That was in the hardware. And that hardware started with the 80386.

    Moreover, the 80286 did NOT have the same instruction set as the 8086. Only in real mode did it. And why do you suppose it was called real mode? Maybe because the addresses were not virtualized? The 80286, as mentioned above, did have virtual addresses in what was called the 80286 Protected Mode. It not only ran Real Mode apps much faster, but when in Protected Mode was very capable of running multitasking Operating Systems, something that could not be done well on the 8086. It also increased the memory bus to 24-bits, albeit still using 64K bit segments.

    OS/2 1.x was the best example of an OS using 286 Protected mode, although any software using "Extended Memory" was taking advantage of the greater addressing of the 286, albeit in an inelegant way.

    I stopped reading after page three, as it's just discouraging to think people are writing books without being accurate. OK, so we have the author that got it wrong, fair enough, but what about the people who are supposed to error check it. I certainly don't know everything, and I know this stuff, and it's pretty basic. No one caught this? Are you kidding me? The 286 stuff might be a bit far away, but not knowing that x86-64 first appeared in the Prescott line is really difficult to understand, and is very basic. This is made more so because of all the rumors that the processor was made to support it, but Intel was hiding it so as to not undercut the Itanium. In time, it was proven true.

    Please, don't spread misinformation. Someone will repeat this stuff, and then someone else will, and it becomes 'fact' despite being wrong. If you publish a book, make a friggin effort! I'm sure I could errors the rest of the way, but it's just too annoying for me to wade through this rubbish.

    By the way, the term CPU bus is an ambiguous one. The CPU has multiple buses, and if you used that term with me, I'd wonder which one you were referring to. Find a more accurate term, like PCI-E bus if that's what you are trying to say.
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