AMD Epyc 'Milan-X' Specifications Emerge in Leak

AMD's yet-unannounced Milan-X server chips have received yet another dose of leaked specifications courtesy of Leaker Executable Fix, including core counts, TDP, and base and boost clocks. Milan-X is expected to be a drop-in replacement for AMD's server platform, with most of its performance and power improvements coming from the 3D V-Cache implementation that's been developed in partnership with TSMC. The chips will join AMD's currently-existing Epyc 7003 portfolio, will be based on the current Zen 3 design, and scale up to 64 cores. As this is a leak, it is best to take the news with a grain of salt until the official launch.

There are a total of four leaked CPUs. The top-of-the-line Epyc 7773X is reported to max out the Zen core count design with 64 cores and 128 threads, a 2.2 GHz base clock, 4.5 GHz boost, and a TDP of 280 W. The usage of 3D V-Cache is where things get interesting, with a grand total of 768 MB being quoted. The 768 MB results from the L3 cache that's part of Zen 3's CCD design (with each 8-core CCD being supported by 32 MB of L3, so, 256 MB in total) as well as the aforementioned stacked V-cache, with an additional 64 MB of L3 cache attached to each CCD (8 x 64 MB = 512 MB). 

Below the Epyc 7773X, AMD is reportedly also saddling three additional models with the 3D V-Cache solution, with the number of cores scaling throughout the stack. The Epyc 7573X should offer 32 Zen 3 cores with a 2.8 GHz base and 3.6 GHz boost clock with the same 280 W TDP; the Epyc 7473X cuts that number down further with only 24 cores, a 2.6 GHz base and 3.7 GHz boost clock at a 240 W TDP; and lastly, the Epyc 7373X, which offers 16 Zen 3 cores at a 3.05 GHz base and 3.8 GHz boost clocks, with the same 240 W TDP. According to the leak, all of AMD's refreshed Epyc Milan-X CPUs will feature the same additional 512 MB 3D V-Cache.

It remains unclear whether these are the only AMD Epyc 7003 series to receive the 3D V-Cache treatment, or if any of AMD's 48-core, 28-core or 8-core models will also be eventually released. The implementation of 3D V-Cache should help in both performance and power consumption: cache serves as a repository for data that the CPU is using or might use for any given workload, and the more data that rests in cache, less latency and power consumption is involved due to the much closer physical proximity of the data to the CPU cores (in comparison to RAM access costs when data is outside of the CPU's cache).