Intel hamstrung by supply shortages across its business, including production capacity — says it will prioritize data center CPUs over consumer chips, warns of price hikes

shady28 said:

Zen 5 is on N4, i.e. a 2nd or 3rd generation 5nm node.

Raptor Lake is on Intel 7, which is essentially equivalent to N7

Your point was monolithic vs. chiplet/tile. Zen 5 has memory latency that's somewhat comparable to Raptor Lake and far better than Arrow Lake. That shows the issue isn't really one of monolithic vs. chiplets/tiles, but rather that Intel just made some bad design choices, when they created the SoC architecture of Meteor Lake & Arrow Lake.

shady28 said:

Raptor Lake still generally beats normal Zen 5 in both games and productivity. Even the 9950X merely trades blows to the 14900K in productivity, while losing in most games.

Games are low-IPC workloads, where Raptor Lake's clockspeed advantage wins the day. AMD doesn't design its CPUs to clock as high, because they share the same silicon with their mainstream server CPUs, where efficiency & scalability targets would rule out anything like the what desktop CPUs can do. So, it makes sense for them to instead focus on designs with slightly lower peak clockspeeds and higher IPC.

Productivity-wise, I don't know what you're talking about, because 9950X wins at:

Source: https://www.techpowerup.com/review/intel-core-ultra-9-285k/
Yeah, I used data from the 285K launch review, in order to avoid the problems reviewers initially had with Zen 5.

shady28 said:

And it shouldn't be a surprise, tiles and chiplets are there to improve yield while providing CPU design flexibility (more chiplets/cores, do I put a 4EU GPU on this or an 8 or a 12, do I give this 4 E cores or 12, etc). They are not there for performance.

You forget about one factor: cost. Chiplets are there as a cost-saving measure, so that parts of the CPU that don't need the latest node don't cost as much. By saving money in some places, more money can be spent elsewhere. Every one of these products is built to hit a certain price target. If you just fab the entire chip on the latest node, then you'd have to cut corners somewhere. Maybe in cache sizes or core complexity, and that would affect performance.

bit_user said:

Your point was monolithic vs. chiplet/tile.

Thanks for reminding me, I had forgotten...

bit_user said:

Zen 5 has memory latency that's somewhat comparable to Raptor Lake and far better than Arrow Lake. That shows the issue isn't really one of monolithic vs. chiplets/tiles, but rather that Intel just made some bad design choices, when they created the SoC architecture of Meteor Lake & Arrow Lake.

<snip a bunch of blather about straw men>

Zen 4/5 along with Zen 2 and Zen 3 along with Arrow Lake, Meteor Lake, and Lunar Lake can all be said to have latency issues compared to monolithic designs like Raptor Lake, or Comet Lake for that matter.

Despite your attempt to turn this into Arrow Lake vs Zen 5, I wasn't talking about Intel vs AMD, nor was I talking about the 285K.

I was talking about tiles/chiplets vs monolithic.

Some quotes and sources on this topic.

"On-chip communication is faster in monolithic designs because the components are physically closer, resulting in lower latency and better overall system performance."
"Monolithic designs often offer superior performance due to the close proximity of components. This proximity reduces signal latency and power consumption, making monolithic chips ideal for high-performance computing."https://resources.pcb.cadence.com/blog/2023-chiplet-vs-monolithic-superior-semiconductor-integration
"The issue with chiplets is that it adds a latency, increases power consumption in addition to the extra cost the interconnects brings."
"On GPUs, the need for extremely low latency has slowed down the adoption of chiplets."https://www.overclock.net/threads/people-keep-saying-chiplets-are-the-future-but-this-just-doesnt-make-any-sense.1801831/
"MCMs with long traces between the CPUs add significant latencies for inter-core communication compared to packing all of these cores in monolithic dies."
https://blog.apnic.net/2023/11/07/chiplets-the-inevitable-transition/
"Although chiplet-based chips can cut (recurring engineering) costs to half, they may give away over a third of the monolithic performance."https://research.chalmers.se/publication/546843/file/546843_Fulltext.pdf

I really shouldn't need to continue at this point.

shady28 said:

<snip a bunch of blather about straw men>

No, it wasn't. I addressed your points and can back up any of them you want me to. I think you either know or suspect I'm actually right, so it's fine with me if you want to drop them. However, don't accuse me of strawmen when they're not.

shady28 said:

Zen 4/5 along with Zen 2 and Zen 3 along with Arrow Lake, Meteor Lake, and Lunar Lake can all be said to have latency issues compared to monolithic designs like Raptor Lake, or Comet Lake for that matter.

Oh, I'm not concerned with what they "can be said to have". People can "say" anything. I'm concerned with actual data, which shows that Ryzen 9000 is competitive with Raptor Lake on DDR5 latency.

Source: https://chipsandcheese.com/p/examining-intels-arrow-lake-at-the?utm_source=publication-search

shady28 said:

Despite your attempt to turn this into Arrow Lake vs Zen 5, I wasn't talking about Intel vs AMD, nor was I talking about the 285K.

You misunderstand. I didn't cite data from the 285K review for the purpose of comparing against the 285K. If you actually look at the charts I included, they all had data for Ryzen 9000 and Raptor Lake. The reason I grabbed the charts from that review was as an easy way to get the latest data on each CPU, not because I was trying to shift the topic to the 285K.

shady28 said:

Some quotes and sources on this topic.

"On-chip communication is faster in monolithic designs because the components are physically closer, resulting in lower latency and better overall system performance."
"Monolithic designs often offer superior performance due to the close proximity of components. This proximity reduces signal latency and power consumption, making monolithic chips ideal for high-performance computing."https://resources.pcb.cadence.com/blog/2023-chiplet-vs-monolithic-superior-semiconductor-integration

Why would I care about random quotes, in the abstract, when we're talking about real world implementations that can be quantitatively measured and compared?

One can talk in generalities all day long, but that ignores what can be achieved via concerted optimization, as AMD has been progressively doing since the days of Zen 2. What matters isn't whether chiplets pose hurdles, but how well you can overcome them, when you really try.

shady28 said:

I really shouldn't need to continue at this point.

It would be pointless to try, unless you have data. General quotes don't prove anything.

bit_user said:

No, it wasn't. I addressed your points and can back up any of them you want me to. I think you either know or suspect I'm actually right, so it's fine with me if you want to drop them. However, don't accuse me of strawmen when they're not.

I just linked you to a university study of the two approaches, yet you insist on your AMD vs Intel blather.

bit_user said:

Oh, I'm not concerned with what they "can be said to have". People can "say" anything. I'm concerned with actual data, which shows that Ryzen 9000 is competitive with Raptor Lake on DDR5 latency.
Source: https://chipsandcheese.com/p/examining-intels-arrow-lake-at-the?utm_source=publication-search

You are talking about main system RAM latencies.

You are also linking to an Intel tile vs AMD chiplet article.

Once again:
I simply stated that monolithic is inherently faster than tiles/chiplets, all else being equal.

Arrow Lake is not monolithic.

bit_user said:

You misunderstand. I didn't cite data from the 285K review for the purpose of comparing against the 285K. If you actually look at the charts I included, they all had data for Ryzen 9000 and Raptor Lake.

They only have that for DRAM. They do not include Raptor Lake for L2/L3 nor most importantly CPU to CPU.

bit_user said:

The reason I grabbed the charts from that review was as an easy way to get the latest data on each CPU, not because I was trying to shift the topic to the 285K.

You've been talking about 285K vs Zen 5 the entire time. Where are your comments about Raptor Lake vs Zen 5?

Or more appropriately, Raptor Lake vs its contemporary Zen 3 on similar process nodes?

bit_user said:

Why would I care about random quotes, in the abstract, when we're talking about real world implementations that can be quantitatively measured and compared?

Because most are from professional trade publications and one is from a university study on the topic at hand : Monolithic vs Disaggregated

bit_user said:

One can talk in generalities all day long, but that ignores what can be achieved via concerted optimization, as AMD has been progressively doing since the days of Zen 2. What matters isn't whether chiplets pose hurdles, but how well you can overcome them, when you really try.

No, the point is that in order to compete against monolithic designs AMD needed an entire node advantage.

Compare Raptor Lake and Alder Lake vs Zen 3, all on N7 / Intel 7 similar nodes and the difference becomes crystal clear.

Unless your judgement is clouded, as yours clearly is.

bit_user said:

It would be pointless to try, unless you have data. General quotes don't prove anything.

As I said, there's an entire university study including simulation examples in those links.

From that study:

Multi-Chiplet vs. Monolithic vs. Ideal: Figure 4 shows,per mix of programs, the average performance (IPC), averagepacket latency, average memory access time, and the breakdown of DRAM accesses for the default configuration of a 4-chiplet system as well as for the equivalent 16-core monolithic and ideal systems. The chiplet-based system is able to maintain only 43%-75% of the monolithic performance and on average 58%, as shown in Figure 4(a). Compared to the ideal system, which is 24% faster than the monolithic, and its LLC misses always go to the closest HBM, the chiplet-based system is 54% slower.

shady28 said:

I just linked you to a university study of the two approaches,

Huge numbers of variables exist in any silicon implementation and there are lots of design choices that weigh on final performance. It's not like you can mathematically prove that any chiplet-based design will perform worse than any monolithic design, hence no study is authoritative.

shady28 said:

yet you insist on your AMD vs Intel blather.

Again, the fact that you try to dismiss my reply as "blather" just indicates that you're incapable of addressing it on the merits. Either way, you lose. But, one way certainly looks worse than the other.

shady28 said:

You are talking about main system RAM latencies.

Right, because cache & memory latency are the dependent variables overwhelmingly determinitive of real-world performance.

shady28 said:

Once again:
I simply stated that monolithic is inherently faster than tiles/chiplets, all else being equal.

I've shown that the inherent downsides of a chiplet-based design aren't insurmountable. That seems to be the key question.

As I've said, all else is never equal. You simply cannot remove practical considerations, like price, from the picture.

shady28 said:

Arrow Lake is not monolithic.

Nobody said it was.

shady28 said:

They only have that for DRAM. They do not include Raptor Lake for L2/L3 nor most importantly CPU to CPU.

Now, you're confused, because I was referring to the TechPowerUp "productivity" charts.

However, Chips & Cheese does have latency data on the cache hierarchies - just not in the table I quoted.

And no, "CPU to CPU" (by which I think you mean core-to-core) latency is not most important. In fact, cores exchange data quite a bit less than they access data in their local cache hierarchy or DRAM. The prominence of those core-to-core latency charts gives a misleading perception of its performance. The real reason why people run those sorts of tests is to divine the interconnect topology and see what kinds of details they can tease out about the cache coherency mechanism, etc.

A multi-threaded program where the cores frequently exchange data would be rife with performance-robbing scalability and lock contention problems, because exchange of data needs to be coordinated. So, skilled programmers try to thread their programs in ways that limit the frequency of data-sharing, as much as possible.

shady28 said:

You've been talking about 285K vs Zen 5 the entire time. Where are your comments about Raptor Lake vs Zen 5?

No, reread the first sentence of post #6, where I pointed out that Zen 5 (by which I meant Ryzen 9000), has memory latency competitive with Raptor Lake. I went on to reply to your points about Raptor Lake with productivity data that included both Ryzen 9950X and i9-14900K.

shady28 said:

Or more appropriately, Raptor Lake vs its contemporary Zen 3 on similar process nodes?

The impact of node choice on DRAM latency is minimal, yet DRAM latency is the most important performance parameter impacted by Ryzen's chiplet-oriented architecture. Furthermore, if you're not convinced by that, consider that Ryzen 9000's I/O Die is implemented on TSMC N6, which has comparable transistor gate pitch and metal pitch as Intel 7. That's also where half of the infinity fabric is implemented, which requests & data must traverse on their way between the cores and DRAM.

shady28 said:

No, the point is that in order to compete against monolithic designs AMD needed an entire node advantage.

As I previously explained, AMD's chiplet-based desktop CPUs are not exclusively or even primarily designed for the desktop. They don't have the luxury of optimizing for clock speed, like Intel does, because that would be transistor-intensive and do little for their primary server market.

You're treating these CPUs as if they have identical design objectives and the only things that differ are chiplet vs. monolithic and process node. This could not be further from the reality. They have countless architectural differences at all scales, and much of that derives from differences in their design objectives and the consequent architectural approaches.

From the first Zen CPUs, AMD focused on scalability, first and foremost. That also came at the expense of clock speed and indeed incurred a latency penalty, but it's one they've worked to minimize as the product line evolved. To see how far that evolution has progressed, we need to look at the latest incarnation, which is Ryzen 9000.

shady28 said:

As I said, there's an entire university study including simulation examples in those links.

Again, this misses the point. Their simulation bakes in numerous assumptions and holds things invariant that wouldn't be, between real world implementations.

Furthermore, the main thing those numbers tell me is that those researchers have no clue how to design a scalable chiplet-oriented CPU. BTW, AMD does make monolithic Zen CPUs. They also make single- and double- CCD chiplet CPUs, and their clock-normalized scaling is nothing like that bad! Your quote also indicates that it's a Zen 1-style NUMA architecture, so of very limited relevance to anything of AMD's which came after, which just goes to show why you can't blindly apply whatever you read in one research paper to some situation that looks kinda similar, if you ignore basically all of the particulars.

If you want to know how well the impact of a chiplet-based SoC architecture can be mitigated, I've already cited that. If you want something else, then I'm not sure I can help you.

Intel has made pricing quite aggressive on Raptor Lake and RL Refresh, so they kind of did this to themselves, lol; I mean, are they after revenues or maintain margin, because my understand was the latter.

I previously mentioned that Intel doesn't even need to have huge capacity on a leading-edge node to maintain good profits -- they just need customers (including Intel as an IFS customer), ensuring fab capacity is close to 100%, and balancing scaling fabs that R&D costs on new nodes is covered by fab revenues. Yes, TSMC makes gobs of money and then can reinvest hundreds of billions of dollars from their sheer scale on leading-edge nodes, but I estimate that Intel can turn a nice profit just by following at N-1 and N-2, even if that's not what we all want (as in "we" wanting Intel to be a TSMC fighter and not a TSMC shadow).