Geopolitical concerns, political pressure from the U.S. government, potential tariffs imposed on semiconductors produced outside of the U.S., and capacity constraints are pushing Apple and Nvidia to consider outsourcing production and packaging of some of their processors to Intel in the U.S., reports DigiTimes. The two companies are reportedly considering outsourcing some of their non-core products to Intel in 2028. Neither of the companies have confirmed the plans.
Apple and Nvidia are reportedly considering using Intel's 18A (or rather 18A-P) or Intel 14A process technology, though it remains to be seen whether Intel has enough advanced capacity for third-party customers in 2028. In addition to the sheer scale of production that Intel must offer to land orders with Apple and Nvidia, it will also have to offer an easy way to port chip designs from TSMC process nodes to its own fabrication technologies, as well as deliver the desired performance and power consumption targets. Yet, keeping in mind that both companies are reportedly looking at Intel primarily due to political pressure, geopolitical concerns, and tariff risks, they might relax some of their demands if key goals are met.
Making Apple's M-series chips at Intel
Apple is reportedly holding discussions with Intel about producing some of its entry-level M-series processors for Mac computers, currently made by TSMC, using Intel instead. While the alleged plan marks a cautious re-engagement with Intel after Apple's transition away from Intel x86 CPUs to its in-house designed custom silicon starting in 2020 and completed in 2022, the renewed talks are driven less by technology considerations and more by geopolitical reasons, cost and tariff concerns, and risk diversification.
Apple's vanilla M-series processors power cost-sensitive laptops and tablets. These CPUs feature relatively small die sizes, relatively cheap packaging, as well as relatively high tolerance for yield and performance variability while being sensitive to costs. Therefore, producing these system-on-chips (SoCs) that are aimed solely at the U.S. market makes sense in the U.S.. Although actual systems are assembled in Asia for now, U.S. policy seems to be semiconductor-centric, not device-centric. Meanwhile, to meet U.S. policy requirements, Apple will have to conduct both silicon production and packaging operations in the U.S.
While Apple's vanilla M-series CPUs are important products for the company, they are not as crucially important as A-series SoCs for iPhones and are not as performance-demanding as M Pro and M Max offerings. Yet, to produce M-series chips at Intel, it is vital that Apple can port its latest micro-architectures to Intel's nodes without major performance degradation to remain competitive on the American market, as this is the key market for the company's popular products like the MacBook Air or iPad Pro.
Packaging Feynman GPUs in America?
Nvidia is reportedly pursuing a similar tactic, but in the case of the AI GPU developer, things are much more complicated. The company reportedly plans to make some of I/O dies for its Feynman GPUs at Intel in the U.S. Furthermore, Nvidia intends to package some (25%) of its Feynman GPUs using EMIB technology at Intel's New Mexico facilities in America, according to DigiTimes. There might be a problem with such an approach, though.
Nvidia's Feynman will likely consume 5 kW – 6 kW of power, points at which traditional board-level voltage regulation will no longer scale, so these processors will require voltage regulator integration (IVR) into advanced packaging (i.e., CoWoS-L interposer). At these currents (we are talking thousands of Amperes here), delivering sub-1V directly from the motherboard leads to severe IR drop, PDN losses, and slow transient response that cannot support aggressive DVFS across large multi-die designs. As a result, building an IVR into packaging enables power to enter the package at a higher voltage (around 1.8 V), which cuts current per bump, improves efficiency, and cuts voltage ripple, while also enabling 10X – 100X faster response than on-board VRMs. To that end, packaging with integrated IVR becomes the primary enabler of performance scaling.
While EMIB can support co-packaged IVR components, as this will not be a true embedded IVR, it will not be enough for a 5 kW – 6 kW AI accelerator. Of course, Intel has Foveros technologies (including Foveros Omni, Foveros Direct 3D, etc.), but these are not direct alternatives to CoWoS-L. While Intel's Foveros technology can certainly support multi-kilowatt power delivery with low IR drop, it does so by vertically stacking dedicated power tiles with logic, which provides extremely fast regulation and fine-grained control. However, this approach prioritizes low inductance and transient response over embedded passive volume, and therefore represents a fundamentally different IVR philosophy rather than a direct analogue to CoWoS-L. To that end, if Nvidia would like to use Foveros Direct3D packaging for Feynman, it would have to redesign the GPU compared to one produced by TSMC for CoWoS-L.
Given complexities with using EMIB and Foveros for high-end data center Feynman GPUs, it is more likely that Nvidia will wait before TSMC brings its advanced packaging to America towards the end of the decade, as it is hardly viable to redesign these large GPUs for Foveros. Still, Intel could probably land packaging orders for Vera CPUs or introduce its custom Xeon CPUs for Nvidia sooner rather than later to land some business from the company it got $5 billion of investment from recently.
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