Nvidia Reveals Next-Generation "Pascal" GPU for 2016
Pascal will use 3D packaging and a new tech called NVLink.
During GTC 2014, Nvidia CEO Jen-Hsun Huang revealed the next-generation GPU, Pascal. This chip is aimed at next-generation super-computers, workstations, gaming PCs and cloud super-computers. The chip is also based on a technology called NVLink, and uses 3D memory to amplify the bandwidth between the GPU and memory sub-system. Pascal fits in a module that's a third the size of a PCIe card.
NVLink is chip-to-chip communications. The programming model is basically PCI Express with enhanced DMA capability, Huang said, and that software can adopt this interface very easily. This solution enables programmers to bind memory between the CPU and GPU, the GPU and GPU, and the second generation cache coherency between the GPU and CPU cache.
"One of the benefits of parallel computing is to be able to take all these GPUs and put them in parallel, and treat them like one big massive GPU. If we'd only have the bandwidth to communicate from GPU to GPU," Huang said during the keynote. "NVLink allows us to do just that."
He also described 3D packaging: for the first time, Nvidia is building heterogeneous chips on top of other chips on a single wafer. This solution starts off with a base wafer where interconnections are carried out among the chips. Thus, instead of going off to a PC board, Nvidia is doing the interchip routing on the wafer itself.
"Thousands of little bumps characterized by that vertical signal on these chips are flipped and bumped onto the base wafer," Huang explained. "The interface went from hundreds of bits to thousands of bits. You can just imagine a GPU with thousands and thousands of memory interfaced bits."
He said Nvidia stacked the memory bits one on top of the other, and punched holes through them. Each DRAM is then stacked on top of each other, all stacked on top of a wafer that can have incredibly small wires that connect to the GPU.
After announcing Pascal, Huang revealed a roadmap with a release schedule for some time in 2016, following Maxwell in 2014 and Kepler in 2012. Thanks to the NVLink and 3D packaging, the company can continue to scale with Moore's Law, Huang said.
nothing new. we know there will be maxwell (in name only) since fermi.
True, Nvidia has always shown us two or three generations ahead on a map of the future. But I don't ever remember them giving this much technical detail before in a product two generations away from the current one.
True, Nvidia has always shown us two or three generations ahead on a map of the future. But I don't ever remember them giving this much technical detail before in a product two generations away from the current one.
i think nvidia are trying to win more contract in the future that's why they are talking stuff that will not coming 2 years later right now. they need to convince those company why choosing nvidia is the right choice. nvidia used to dominate the HPC stuff with their Tesla but now they got more competition from AMD and Intel (Xeon Phi) in that space. releasing a bit of info about upcoming architecture could be one of their strategy
from what i understand this NVLink is for HPC and server stuff only although there are possibility for nvidia to incorporate this tech into their SLI technology. maybe they can make something similar to NF200 chipset.
http://techreport.com/news/26226/nvidia-pascal-to-use-stacked-memory-proprietary-nvlink-interconnect
EDIT: from anandtech article it seems NVLink will ditch PCI/PCIE slot altogether and will have it's own connector. so i don't think we are going to see NVLink on regular dekstop mobo.
http://www.anandtech.com/show/7900/nvidia-updates-gpu-roadmap-unveils-pascal-architecture-for-2016