IBM releases complete Cell v. 1.0 specifications

Hopewell Junction (NY) - With less than a minimum of fanfare, IBM today released the complete version 1.0 specification for its forthcoming Cell processor, or as the company now calls it, the "Cell Broadband Engine." IBM will be producing this graphics-intensive CPU in cooperation with Sony and Toshiba.

What Intel calls "cores" in a processing engine, IBM calls "elements;" and IBM's counterpart to what Intel called "NetBurst" in Pentium 4, is referred to as "CBEA." So it may, at some point, become politically incorrect to refer to Cell as a "multicore" processor. Nonetheless, as previously anticipated, the specification mandates that a CBEA-compliant processor must contain at least one of two types of processing elements: a PowerPC processor and a secondary type called the synergistic processor element (SPE). Like the co-processor of ancient days, an SPE is subordinate to the PowerPC element, and performs no system management functions whatsoever. Instead, it can be delegated user-specific tasks, especially graphics processing, which can take advantage of the SPE's Single Instruction/Multiple Data (SIMD) architecture.

As the Cell 1.0 spec confirms, the SPEs utilize "true SIMD" architecture. Here, a single control unit can direct a multitude of slave arithmetic units to execute the same category of instruction on multiple data elements simultaneously. The "true" part of Cell's SIMD implementation lies in the simultaneous execution: In graphics cards, multiplexing of instructions takes place through pipelines, which address different elements of memory in sequence, often by offsetting an index with each iteration. In Cell's true SIMD, all the arithmetic units are given their marching orders, where they march in unison rather than single-file.