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More On Bobcat

AMD’s Bulldozer And Bobcat Architectures Pave The Way
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AMD had a bit more to add on its Bobcat design, unquestionably created with the Fusion initiative in mind. The focus here is on Bobcat as a technology, which AMD plans to use to create SoCs targeting specific markets—the first of which should be its Ontario APU, featuring on-die graphics processing, fixed-function video playback acceleration, a DDR3 memory controller, and the dedicated bus linking everything together.

AMD’s estimate here is retention of 90% of today’s mainstream performance (I’d certainly consider something in Athlon II territory reasonable) in less than half of the silicon area. That’s a figure we’ve seen AMD use in past discussions of Bobcat. But perhaps less known was how the company planned to achieve this.

Details being discussed today include a dual-issue x86 decoder and out-of-order execution, perhaps enabling a performance advantage compared to Intel’s Atom CPUs. Bobcat will support SSE, SSE2, and SSE3, along with virtualization acceleration.

Beyond its performance implications, though, AMD repeats over and over that this is a sub-1 W-capable core. Possible though that might be (at standby), remember that Ontario will incorporate a pair of these cores. Additionally, Bobcat is part of a SoC. So, it might be a little more realistic to expect power numbers between 10 and 20 W.

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