Loongson Rips MIPS: Uses Old Code for New CPUs

Even though Loongson claims that its latest 3A5000 and 3C5000 processors are based on its in-house developed proprietary architecture and no longer rely on the MIPS architecture, the code the company uses to enable the new CPUs in Linux is actually the same code it used for its MIPS-based chips. Furthermore, the CPU developer fails to demonstrate advantages of its architecture even on paper to software developers. 

Historically, Loongson's CPUs relied on various types of the company's LoongISA architecture, a custom subset of the MIPS64 architecture. Such a tactic enabled the company to preserve compatibility with programs designed for MIPS64 (which includes software for high-performance computing applications) while bringing in its own extensions to improve performance in contemporary applications. 

"You keep saying 'not MIPS,' and yet all I see is a blind copy of the MIPS code," a software developer wrote to Loongson. "This is still the same antiquated, broken MIPS code, only with a different name." 

"What is that? Yet another MIPS legacy? Why does it have to be per interrupt if it obviously apply to each and every root interrupt?" another developer wondered. "You still obviously have some static partitioning of the interrupt space, which is not acceptable for a new architecture."

Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.