RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint

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ARM has some competition in the reduced-complexity chip space, and it's gaining ground quickly. RISC-V International plans to announce that silicon on the open-standard has reached 25% market penetration later this month, according to an announcement posted to LinkedIn. Market analysts SHD Group are primed to announce their findings on RISC-V market share at the RISC-V Summit North America.

RISC-V is an open-standard (not to be confused with open-source) instruction set architecture (ISA) for CPUs, first established in 2014. For those unfamiliar, an instruction set architecture is a technical model that determines how computer software controls the computer’s processor. The ISA defines what instructions a processor can perform in order to output computations. RISC-V, a reduced-complexity ISA, is most closely related to ARM, also a RISC, known for powering most mobile and some laptop devices.

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Just last year, Omdia predicted that RISC-V would hit 25% share of the entire semiconductor market in 2030, reaching 17 billion chips shipped in 2030. Now the SHD Group's forthcoming estimates raise this number to 21+ billion chips by 2031, eclipsing $2 billion in total revenue by this point. RISC-V International credits this increase in growth to RISC-V's use in Edge AI deployments, referring to more localized data hubs serving smaller communities, rather than sending all work to a general cloud hub.

RISC-V’s most essential distinguishing factor is that it is an open standard. Working groups and tech firms can access, use, and iterate on the RISC-V standard for free, without paying licenses or entering into contracts with the RISC-V governing body. Arm, on the contrary, makes money off licensing the ARM instruction set and pre-designed CPU cores to client firms and chipmakers, offering closer support to client companies while also receiving royalties from the use of its designs. This increased collaboration and community contribution have been a major hallmark of RISC-V's continued growth.

The full picture of the 25% market estimate will be unveiled in a keynote address at the RISC-V Summit North America, beginning in Santa Clara, CA, on October 21st. Other speakers at the Summit will include Google, AWS, and NASA, all perennial attendees of the summits. RISC-V has also received much attention from Meta lately; the Facebook company acquired the RISC-V GPU firm Rivos last week in pursuit of its own RISC-V-based AI accelerator.

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Sunny Grimm is a contributing writer for Tom's Hardware. He has been building and breaking computers since 2017, serving as the resident youngster at Tom's. From APUs to RGB, Sunny has a handle on all the latest tech news.

2 Comments Comment from the forums

bit_user

Nice article!

The article said:
RISC-V’s most essential distinguishing factor is that it is an open standard. Working groups and tech firms can access, use, and iterate on the RISC-V standard for free, without paying licenses or entering into contracts with the RISC-V governing body.
Just wanted to note one thing: RISC-V is also very extensible. The instruction op code space is organized to accommodate many extensions, including vendor-specific extensions. This makes it popular for embedded usage, where a device maker can quickly and easily add custom functionality via a block of instructions specific to their implementation or application needs.
https://en.wikipedia.org/wiki/RISC-V#ISA_base_and_extensions
Contrast this to something like ARM, where the instruction set is tightly controlled by ARM and even implementers with their own "Architecture Licenses" (e.g. Apple, Qualcomm) are not allowed to add custom instructions (although ARM does routinely add both optional and mandatory blocks of new opcodes).

This ability to customize your own implementation complements the potential to create your own RISC-V designs, without having to secure approval or a license from anyone, to make RISC-V an ISA which prioritizes freedom and flexibility. Yet, the benefit of being a ISA standard is that you get tools & OS support almost for free, if you merely adhere faithfully to particular baseline functionality.
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brucehoult

bit_user said:

This ability to customize your own implementation complements the potential to create your own RISC-V designs, without having to secure approval or a license from anyone, to make RISC-V an ISA which prioritizes freedom and flexibility. Yet, the benefit of being a ISA standard is that you get tools & OS support almost for free, if you merely adhere faithfully to particular baseline functionality.
Right, and having complete compatibility with C/C++/Rust compilers requires implementing as few as the 37 core RV32I instructions in 4 basic formats for an embedded microcontroller core, or 47 instructions for a 64 bit microcontroller. That might well be all you need, or you can add whatever standard or custom extensions make sense in your application.

There is really very little reason -- and huge costs -- for someone to make up their own proprietary ISA for basic integer functionality.

RISC-V has already killed off use of "minnow" 32 bit ISAs in new projects. All major FPGA vendors now have officially supported RISC-V soft cores as the "new version" of their traditional proprietary soft cores.

Multi-cycle implementations of RISC-V with 1, 4, 8 bit bus/ALU widths compete well with even 8 bit cores in LUT/gate usage and execution speed, while providing the advantages of a 32 bit ISA and full optimising compiler support. I don't think anything is going to survive except maybe 8051 as it is 45 years old, out of protection, widely cloned, and better suited to its niche than similar vintage cores such as 6502 or z80. And I'm not even sure about 8051.
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