TSMC's average wafer prices increased by over 15% each year since 2019, report suggests — gross profit margins increase by 3.3x in 2025 alone, facing no real challengers

TSMC's average selling prices (ASPs) for its wafers have increased 15.9% annually from 2019 to 2025. Additionally, gross profit margins per wafer rose rapidly to 3.3x throughout 2025, according to SemiAnalysis. This increased margin reflects TSMC fully leveraging its market-leading position and broad ecosystem to command higher product pricing, which in turn drives downstream effects, including higher end-product pricing. The increases come after a decade during which TSMC earned minimal profit, keeping pricing low as it cornered the market and expanded its market share.

The new era of extreme ultraviolet (EUV) chipmaking began in 2019, with TSMC positioned as the top contract chipmaker. Equipped with robust production capacity and an ecosystem of partners leveraging this new technology, TSMC has seen significant ASP growth. The company is expected to maintain this momentum into 2026 and beyond, driven by several factors.

The rise of TSMC

Since its inception in 1987, through to the 2010s, TSMC was considered a leading foundry, but not a leading chipmaker. At the time, Intel was the undisputed champion of the semiconductor industry, with microelectronics pioneers like IBM also remaining competitive. However, TSMC has been consistently expanding its ecosystem over the years. In 2008, the company established its Open Innovation Platform (OIP) program — uniting TSMC with chip designers, IP providers, and EDA tool developers — essentially setting the stage for its current success.

Things changed suddenly for TSMC in the mid-2010s, when Apple outsourced production of its chips to TSMC, departing from Samsung, which had since become a significant rival to Apple in the smartphone segment. For Apple, going with TSMC guaranteed no IP theft and no plans to compete in the smartphone segment. TSMC also offered a continually evolving roadmap of process technologies and capacity availability, which, among other things, persuaded Apple to back TSMC.

Landing orders from the world's largest manufacturers of consumer electronics (including Huawei, Sony, and Panasonic) gave TSMC the financial capacity required to invest in R&D and new tools to produce chips for customers at high volumes. With Intel's hiccups with its 10nm fabrication process, TSMC entered 2019 with all of the factors needed to become a market leader.

The company was offering services that no other chipmaker could match, bagging big-name customers like Apple, Huawei, and Nvidia in the process. This offered TSMC not only informal recognition of leadership but also the financial resources to expand its turf.

Expensive tools? Even more expensive chips

As a result, after more than a decade of stagnation, TSMC's wafer pricing model fundamentally changed in 2019, as it had to buy, deploy, and depreciate ASML's Twinscan NXE tools, which cost around $235 million each. While these tools from ASML were less expensive in 2019, they steadily increased in price, as the machines became more advanced.

Since TSMC had no real competition, and an increase in the costs of machinery, these factors set the stage for market dominance. Paired with the massive OIP infrastructure, TSMC managed to expand gross profit per wafer by roughly 3.3x throughout 2025, based on data from SemiAnalysis. The report claims that quotes are rising at a far faster pace than production costs, which sets a new economic baseline for leading-edge foundry manufacturing.

EUV revolutionizes fab industry

From 2005 to 2019, TSMC's wafer ASPs remained largely flat because leading-edge foundry capacity was still relatively elastic due to competition, according to SemiAnalysis. Over those 15 years, ASPs increased by only $32 per wafer, with an annual growth rate of approximately 0.1%. Process nodes advanced rapidly using DUV lithography, so capital intensity increased gradually (i.e., in accordance with the growth of customer requirements) rather than exponentially.

During this period, the company largely operated under a cost-pass-through model, using modest pricing adjustments to offset rising manufacturing expenses. This approach limited margin expansion even as process complexity increased. Consequently, market conditions dictated wafer pricing, rather than the capital requirements of foundries.

However, customer economics limited this value-based pricing. Leading-edge demand was dominated by smartphones and consumer SoCs with tightly constrained bill-of-materials (BOM) targets, and no ballooning AI or HPC segment was generating massive gross margins. Yield learning curves were rapid; performance-per-watt gains were predictable; tool and mask costs were rising at a pace that allowed rivals to follow TSMC with capacity and competitive nodes; and there was no structural shortage of production capacity.

As a result, TSMC, just like other foundries, prioritized utilization, scale, and long-term ecosystem dominance over margin expansion. This strategy kept ASP growth near zero until TSMC began to adopt EUV for high-volume manufacturing, forcing their hand and intensifying capital expenditures. These factors coincided with the beginning of the AI and HPC megatrends we've observed in recent years.

In the six years that followed, wafer ASPs at TSMC rose by approximately 133%, equivalent to a 15.2% compound annual growth rate, while the cost of goods sold increased by only 78%. As a result, TSMC's gross profit per wafer increased sharply. Regression analysis made by SemiAnalysis illustrates the shift clearly: before 2019, every $1 increase in cost of goods sold (COGS) translated into $1.43 in ASP, yielding $0.43 in incremental profit; after 2019, the same $1 cost increase generated $2.31 in ASP, or more than $1.30 in incremental profit.

As noted above, the inflection coincided with the industry's transition to EUV-based process technologies, which dramatically altered supply dynamics, as TSMC became the only viable choice for big companies. While Samsung began using EUV tools for HVM in 2018, it used them only for its own chips, primarily due to tool scarcity and yield constraints.

The use of EUV tools at TSMC increased capital intensity and slowed capacity expansion, as EUV systems are physically larger than older DUV scanners and place their light source beneath the tool, making the addition of leading-edge output even more difficult. As a result, advanced-node wafers ceased to be interchangeable commodities and became capacity-constrained assets for tens of competing high-tech giants.

This allowed TSMC to price its output well above incremental cost without eroding demand. AI and HPC processors produced for customers like AMD, Broadcom, Google, Intel, or Nvidia carry significantly higher margins than legacy mobile or consumer chips. As a result, TSMC anchors pricing to customer value rather than manufacturing expense, which highlights the post-2019 divergence between ASP growth and COGS inflation.

In fact, big customers like AMD, Broadcom, Nvidia, and Marvell are willing to pay TSMC extra to lock in production capacity with the best process technologies to produce AI accelerators.

Advanced packaging further strengthened TSMC's position. By integrating leading-edge logic with sophisticated packaging technologies, the company increased customer lock-in and raised barriers for competitors. Notably, rising wafer costs now work in TSMC’s favor by discouraging new entrants and widening the competitive moat, rather than compressing margins as they did in earlier eras.

A new foundry model

The data published by SemiAnalysis indicates that TSMC has transitioned from a traditional foundry model focused on scale, utilization, and cost recovery to one defined by systematic undersupply, extreme capital intensity, and value-based pricing.

Leading-edge wafers are no longer commodities that can be obtained from multiple sources, but constrained assets required by trillion-dollar corporations. Given the current situation, pricing is increasingly anchored in the economic value delivered to customers rather than in incremental manufacturing costs. As a result, TSMC is thriving, and it will continue to do so until a viable challenger emerges. Neither Intel Foundry nor Samsung Foundry can currently compete against TSMC's leading-edge production capabilities, at least not yet.

It should be noted that TSMC's pricing power did not appear overnight. It emerged after decades of sustained capital investment, consistent yield leadership across successive nodes, and the gradual consolidation of the industry's most valuable supplier onto a single chip development and manufacturing platform under the OIP brand. Also, TSMC has attracted most of the world's leading chip designers, including Intel, which has its own manufacturing capacities.

These factors created both technical and economic lock-in, resulting in rising costs that reinforce competitive barriers rather than shrinking margins. This highlights a fundamental reality of advanced semiconductor manufacturing in general: TSMC's lasting pricing power has emerged from long-term structural investments along with stable performance increases and yields, and cannot be replicated in the short term.