Silicon Motion announces new devices at Future of Memory and Storage summit 2025: PCIe 6.0 SSDs, 256 / 512 TB drives, and next-gen 16K LDPC
Bigger drives, a new controller, and a larger LDPC enabled by new tech.
Silicon Motion's program at the ongoing Future for Memory and Storage (FMS) conference was packed with announcements. The company offered a glimpse at controllers for PCIe 6.0 SSDs for consumer and data center applications, shared details on the evolution of its MonTitan SM8300-series PCIe Gen5 platforms for enterprise SSDs, and discussed next-generation Low Density Parity Check (LDPC) implementations with a 16K codeword.
PCIe 6.0 SSDs for data center applications
The pinnacle of Silicon Motion's SSD controllers is its upcoming MonTitan SM8466 controller for data center SSDs, sporting a PCIe 6.x x4 host interface. The NVMe 2.0-compliant controller features 16 NAND channels, enabling SSDs with capacities of up to 512 TB, as well as unprecedented sequential performance of 28 GB/s and random performance of 7 million 4K IOPS.
In addition to offering very high raw performance, the MonTitan SM8466 platform also features controller-level and firmware-level architectural enhancements that the company says reduce latency, increase real-world bandwidth, and enable predictable QoS-compliant performance in various workloads.
One is called Separate Command Architecture (SCA), which separates command and address transmission paths within the NAND interface. This enables it to transmit data in parallel (rather than sequentially), reducing latency and improving throughput.
Another is named Performance Shaping (which might be a new name for PerformaShape on existing enterprise-grade controllers, with some upgrades), which appears to be a method designed for SSDs to regulate their behavior to deliver stable, predictable, and QoS-compliant performance even under complex, burst-like workloads. Performance Shaping can also be tuned for specific tasks, depending on requirements.
The MonTitan SM8466 is designed to meet the requirements of NVMe 2.0+ and the OCP NVMe SSD Specification 2.5, aligning it well with the demands of cloud-scale and hyperscale environments. To offer maximum reliability with upcoming generations of NAND.
The controller also supports an LDPC ECC with a 4KiB codeword and 16KiB Collaborative Codeword (CoCo), which is a breakthrough for Silicon Motion, which we will explain in further detail below.
The platform supports virtualization technologies such as SR-IOV and MPF, alongside SMART diagnostics and comprehensive data protection. On the security front, the drive features Secure Boot, AES-256 encryption, TCG Opal compatibility, and firmware attestation—providing a robust suite of protections for mission-critical enterprise data.
Wallace Kou, chief executive of Silicon Motion, expects partners to begin shipping SM8466-based SSDs in late 2026 or early 2027, aligning with the rollout of next-gen AI servers using Nvidia's Rubin GPUs. SMI sees AI as the primary early use case for PCIe Gen6 SSDs, while broader storage adoption in general-purpose servers is not expected until 2026 or 2027. PCIe 6.0 SSDs for consumer PCs are unlikely to appear before 2030.
PCIe 6.0 SSDs for consumer applications aren't coming soon
Silicon Motion formally introduced its first controller for SSDs with a PCIe 5.0 x4 interface a couple of years later than its rival Phison, which certainly affected its position in the market for enthusiast-grade drives. With next-generation PCIe 6.0 SSDs, the company is acting completely differently, so it gave a sneak peek at its new controller, codenamed "Neptune," at FMS 2025.
Silicon Motion's Neptune controller is the first announced PCIe 6.0 x4 SSD platform aimed at consumer PCs; it features eight NAND channels with interface speeds up to 4800 MT/s to support upcoming 3D NAND generations with over 400 active layers. The controller promises to enable sequential read speeds exceeding 25 GB/s and random performance of 3.5 million IOPS, far surpassing today's best PCIe 5.0 consumer SSDs. Additionally, the controller also incorporates Separate Command Architecture (SCA) to reduce latency and increase bandwidth.
Despite its performance gains, SMI says Neptune will still trail the enterprise-grade SM8466 in sequential reads and offer half the random IOPS, as the latter uses 16 NAND channels and additional optimizations for sustained throughput.
The exceptional performance of PCIe 6.0 x4 SSDs will come with a premium. PCIe Gen6 SSD controllers need significantly more processing power to enable compatibility with the next generations of 3D NAND memory. PCIe Gen6 SSD controllers will also need to work with upcoming 3D NAND at higher interface speeds without performance degradation.
Additionally, PCIe 6.0 controllers and PHY are harder and more expensive to implement than PCIe 5.0 counterparts.
Mass production of Silicon Motion's Neptune is scheduled for 2028, with drives likely hitting the market in 2029 or 2030, which aligns with earlier remarks by Silicon Motion CEO Wallace Kou.
"You will not see any PCIe Gen6 [solutions] until 2030," said Kou in an interview with Tom's Hardware. "PC OEMs have very little interest in PCIe 6.0 right now — they do not even want to talk about it. AMD and Intel do not want to talk about it."
16KiB Collaborative Co LDPC
In addition to performance and capacity gains promised by enterprise-grade MonTitan SM8466, there is a crucially important capability that enables extreme performance, high capacities, and exceptional reliability required by data center solid-state drives: Silicon Motion's 16KiB CoCo LPDC ECC technology.
As 3D NAND devices gain more layers, their cells get physically smaller, and the number of bits stored per cell increases from one in SLC to four in QLC. Such advancements enable higher density and lower cost per terabyte, but they also make it harder to retrieve data reliably, especially over prolonged retention periods.
Smaller cells store less charge per bit, which makes them more susceptible to retention loss, program/erase wear, or read disturb. For enterprise SSDs that must meet multi-year endurance and retention requirements, stronger error-correction codes (ECC) are crucial.
Traditional Low-density Parity-check (LDPC) designs use a fixed codeword length — for example, a 4 KiB LDPC, where each 4 KiB of NAND data is encoded and decoded independently. Typically, the longer the codeword, the better the SSD's error-correction strength and endurance.
However, this is at the cost of decode latency, compute requirements, and power consumption. Moving to a 16 KiB LDPC increases the number of parity bits available per unit of data, which significantly improves error-correction strength. This is required for long-term retention and reliability targets in 3D TLC NAND and 3D QLC NAND-based enterprise SSDs. However, while a 16 KiB LDPC ECC is very good, it is costly in terms of compute (i.e., die size and costs), latency, and power, so Silicon Motion opted to utilize a different technique.
The 16 KiB Collaborative Codeword (CoCo) LDPC technique aims to capture most of the reliability benefits of 16 KiB LDPC without significant penalties, according to the company.
In CoCo, a 16 KiB NAND page is divided into four independent 4 KiB LDPC codewords, so each chunk is decoded separately, and most reads behave like a rapid, standard 4 KiB LDPC. If one or more chunks fail to decode, the successful chunks provide 'helper' information that is fed back into the LDPC decoder for the failed chunks. Depending on the CoCo configuration, the system can recover from one up to all four chunks failing, with reliability approaching that of a true 16 KiB LDPC, according to Silicon Motion.
This hybrid design enables Silicon Motion to build an enterprise-grade SSD controller for ultra-high-capacity 3D QLC NAND SSDs with enterprise-grade endurance, while keeping decoder complexity and power usage close to a 4 KiB design. The solution also preserves small-IO latency for random reads (which is critical in mixed workloads) while also delivering the stronger error-correction needed for high-capacity drives.
To sum things up, SMI's 16 KiB CoCo LDPC delivers a near-equivalent to a 16 KiB LDPC, but with the performance, cost, and efficiency of a 4 KiB LDPC. Initially, Silicon Motion's clients will use 16 KiB CoCo LDPC technology for high-performance, high-capacity drives based on the MonTitan SM8466 controllers.
If they do not need extreme capacity or high-density 3D QLC NAND, they will be able to stick to regular 4 KiB LDPC. Eventually, 16 KiB CoCo LDPC ECC will likely move to mainstream enterprise drives and perhaps even consumer drives, but it's simply too early to tell.
256 TB PCIe Gen5 SSDs
Over the past few weeks, we saw a number of companies announcing 245TB or 256TB SSDs based on custom controllers. This week, Silicon Motion announced that its proven MonTitan SM8366 controller now supports capacities up to 256TB using the latest generation 2Tb 3D QLC NAND devices, which is a twofold increase compared to existing SSDs based on the same controller.
Of course, makers of enterprise SSDs will have to qualify 2Tb 3D QLC NAND devices with the SM8366 platform, so 256 TB SSDs based on a standard controller are not expected to be released soon. Nonetheless, these high-capacity drives are expected to become more widespread several quarters from now, which will create competition and inevitably affect pricing.
Next-gen devices are almost here
Silicon Motion used Future for Memory and Storage (FMS) conference too unveil its PCIe 6.0 SSD controller roadmap, led by the MonTitan SM8466 for data centers with up to 512 TB capacity, 28 GB/s reads, 7 M IOPS, and new features. However, the most crucial announcement was the 16 KiB CoCo LDPC ECC, on the MonTitan SM8466. This offers a near-equivalent to the correction power of a 16 KiB LDPC ECC, but with the performance, cost, and efficiency of 4 KiB LDPC. This will be particularly useful for 512TB SSDs based on 3D QLC NAND memory.
While consumer PCIe 6.0 controllers are not expected for some time to come, the announcements present breakthroughs that are anticipated to land in the months and years ahead.
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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.