PCI Express 3.0: The Timeline
Al Yanes, president and chairman of PCI-SIG, and Ramin Neshati, chairman of the PCI-SIG Serial Communications Workgroup, addressed the current timeline of PCI Express 3.0 development.
On Wednesday, June 23rd, PCI Express 3.0 revision 0.71 was released. Yanes stated that the 0.71 release marks what is believed to be the resolution of the backward compatibility issues that had caused an initial delay. Neshati described the primary compatibility issue as “DC wandering,” which he explained as PCI Express 2.0 and earlier devices “not having enough zeros and ones” to satisfy the demands of the PCI Express 3.0 interface.
Now that the backward compatibility issues are resolved, the PCI-SIG says it is on track for the base release of the 0.9 revision “later this summer.” This is expected to be followed by the base release of revision 1.0 in the fourth quarter of this year.
Of course, the most pressing question is when can we can expect to see PCI Express 3.0-based motherboards on store shelves. Neshati stated that he expects to see initial products in the first quarter of 2011 (the “FYI” triangle on the Timeline image).
Neshati added that there would be “no silicon-impacting changes” (the only changes would be software/firmware-related) between revision 0.9 and revision 1.0, which is what will allow some products to start to trickle into the marketplace before the final release of the 1.0 revision. During this time, products will be able to qualify for the PCI-SIG “Integrator’s List” (the “IL” triangle), which is PCI-SIG’s version of an approval logo.
Neshati jokingly referred to the third quarter of 2011 as the “Fry’s and Buy” date (an apparent reference to Frys.com and either Buy.com or Best Buy). This is the time in which we can expect to see a large selection of PCI Express 3.0-based merchandise for sale on the Web and in retail stores.