The primary difference for end users between PCI Express 2.0 and PCI Express 3.0 will be a marked increase in potential maximum throughput. PCI Express 2.0 employs 5 GT/s signaling, enabling a bandwidth capacity of 500 MB/s for each “lane” of data traffic. Thus, a PCI Express 2.0 primary graphics slot, which typically uses 16 lanes, offers bidirectional bandwidth of up to 8 GB/s.
PCI Express 3.0 will double those numbers. PCI Express 3.0 uses an 8 GT/s bit rate, enabling a bandwidth capacity of 1 GB/s per lane. Accordingly, a 16-lane graphics card slot will have a bandwidth capacity of up to 16 GB/s.
On the surface, the increase from 5 GT/s to 8 GT/s doesn’t quite sound like a doubling of speed. However, PCI Express 2.0 uses an 8b/10b encoding scheme, where 8 bits of data are mapped to 10-bit symbols to achieve DC balance. The result is 20% overhead, cutting effective bit rate.
PCI Express 3.0 moves to a much more efficient 128b/130b encoding scheme, eliminating the 20% overhead. So, the 8 GT/s won’t be a “theoretical” speed; it will be the actual bit rate, comparable in performance to 10 GT/s signaling with 8b/10b.
PCI-SIG states that it chose the route of eliminating overhead instead of increasing to 10 GT/s because “8 GT/s represents the most optimal tradeoff between manufacturability, cost, power, and compatibility.” The group further states that bumping the speed to 10 GT/s creates “prohibitive penalties” including “design complexity and increased silicon die size and power.” PCI-SIG’s Al Yanes added, “The magic is in the electrical stuff. These guys have really come through for us.”
I asked Yanes what devices he anticipates will require the increase in speed. He replied that these will include “PLX switches, 40 Gb Ethernet, InfiniBand, solid state devices, which are becoming very popular, and of course, graphics.” He added “We have not exhausted innovation, it’s not static, it’s a continuous stream,” clearing the way for even more enhancements in future versions of the PCI Express interface.