It feels like a bad nightmare. Intel's LGA1200 socket for Comet Lake (opens in new tab) processors isn't even a year old yet, and there are already talks of a new socket for next year's 10nm processor.
The latest Intel document (via @momomo_us (opens in new tab)) seemingly confirms that 12th Generation Alder Lake processors willprobably land with the LGA1700 socket. Alder Lake-S refers to the desktop processors, while the Alder Lake-P is a mystery for now.
Intel's nomenclature for its sockets has remained unchanged over the years. As the name implies, the LGA1700 socket will likely come with 500 more pins, which represent a 41.7% pin increase over the existing LGA1200 socket. It'll be interesting to see how Intel distribute the additional pins, and whether LGA1700 socket proves to be wider or longer than the LGA1200 socket.
Normally, the excess pins are there to deliver more power to the processor, support new features or expand I/O capabilities. In Alder Lake's case, it could be all of the aforementioned. Intel's recent Lakefield processors (opens in new tab) brought a hybrid design that combines powerful cores with energy-efficient cores, similar to Arm's big.LITTLE microarchitecture. The current buzz around town is that Alder Lake could bring this same concept to the desktop, and that's seemingly confirmed by a recent HWinfo update that lists Alder Lake as a "hybrid CPU," which is Intel's nomenclature for the big.LITTLE-esq implementation in Lakefield.
Lakefield blends one big core with four smaller cores into a five-core package. Alder Lake, on the other hand, could break cover with a 16-core design that merges eight big cores with eight small cores. Lakefield employs Sunny Cove and Tremont for the high-performance and low-powered cores, respectively.
Alder Lake might utilize a combination of Golden Cove and Gracemont cores, the first being the successor to Willow Cove and the latter for Tremont. However, there isn't any evidence that remotely backs up this hypothesis. The rumored thermal limit for Alder Lake is 125W and if so, it would be on the same grounds as Comet Lake.
There are a lot more hearsay on Alder Lake, and for now, we should take them with a pinch of salt. In terms of support, Alder Lake allegedly welcomes the PCIe 4.0 interface and DDR5 memory. Being a 10nm part, Alder Lake likely leverages Intel's Xe graphics, but it's unclear which generation of the iGPU will be featured inside the chip.
It has to increase in size given the number of new pins.
That means you'll probably need a new spec for coolers to mount to along with more surface area for the heat spreader.
That means all old LGA 1200/115x coolers will be obsolete.
Still, there's nothing new. After Comet Lake comes Rocket Lake. And that's two generations, which means it's time for a new desktop socket. That's how Intel rolls.
The only exception to that was Haswell, which launched with a new socket that only lasted 1 generation, since the Broadwell desktop CPUs were pretty much all cancelled.
Intel even went so far as to introduce some trivial incompatibilities between Kaby Lake and Coffee Lake. Not to say that the new socket delivered no benefits, but a few boards have been made supporting all 4 generations - from Skylake to Coffee Lake-R, showing just how minor the differences must really be. Why they went ahead with it is anyone's guess - no doubt power-delivery was one reason, but AMD seems to have addressed such matters without changing their socket. So, perhaps it was motivated by wanting to keep commitments to their board partners and force a few extra sales?
As for the function of the 500 additional pins, I'm going to speculate that it could have something to do with Thunderbolt / DP 2.0 / USB 4.
If we consider that each "little" core is about 60% as fast a "big" core, yet uses about 40% of the area and maybe only 30% of the power, then it's both a more power- and area- efficient way to scale performance for highly-threaded workloads. Plus, they get better idle power numbers, by running backgound tasks on the "little" cores.
And all of the necessary software support should already be in place for Lakefield.
When you look at it like that, it really seems pretty obvious. Of course, I pulled the numbers out of the air, but I believe they're in the general ballpark, based on the slides they published (and other available info) on Lakefield.
As for what the 500 pins might be for, my guess is Intel has brought the chipset on-package, so ~300 of those pins are HSIO lanes with their associated power/ground pins and the bulk of the remaining 200 pins are for chipset power.
...there's no indication of HT. I think only the first-gen Atom cores had Hyperthreading. Tremont is now about the 5th major revision of the uArch, not counting node-shrinks and lumping Goldmont/Goldmont+ together.
BTW, I noticed the article mentioned Gracemont - the one after Tremont - but Wikichip has basically nothing on it.
For software to support "heterogeneous processing" of a common task between CPUs + GPUs, the code has to be separately compiled for each, and software has to explicitly manage sharing of the workload between them. It doesn't come for "free", like in the big+little scenario. I'm sure you know this, but I'm just explaining for the benefit of others.