A recent patent published by Intel (via Underfox) may be the keystone for its future graphics accelerator designs - and it utilizes the Multi-Chip Module (MCM) approach. Intel describes a series of graphics processors working in tandem to deliver a single frame. Intel's design points towards a hierarchy in workloads: a primary graphics processor coordinates the entire workload. And the company frames the MCM as a whole approach as a required step to guide silicon designers away from manufacturability, scalability, and power delivery problems that arise from increasing die sizes in the eternal search for performance.
According to Intel's patent, several graphics draw calls (instructions) travel to "a plurality" of graphics processors. Then, the first graphics processor essentially runs an initial draw pass of the entire scene. At this point, the graphics processor is merely creating visibility (and obstruction) data; it's deciding what to render, which is a high-speed operation to do on modern graphics processors. Then, a number of the tiles generated during this first pass go to the other available graphics processors. According to that initial visibility pass, they would be responsible for accurately rendering the scene corresponding to their tiles, which indicates what primitive is in each tile or shows where there is nothing to render.
It thus seems that Intel is looking at integrating tile-based checkerboard rendering (a feature used in today's GPUs) alongside distributed vertex position calculation (out of the initial frame pass). Finally, when all graphics processors have rendered their piece of the puzzle that is a single frame (including shading, lighting, and raytracing), their contributions are stitched up to present the final image on-screen. Ideally, this process would occur 60, 120, or even 500 times per second. Intel's hope for multi-die performance scaling is thus laid bare in front of us. Intel then uses performance reports from AMD and Nvidia graphics cards working in SLI or Crossfire modes to illustrate the potential performance increases in classical multi-GPU configurations. But, of course, it will always be lower than an authentic MCM design.
Intel's patent is fuzzy in details as to the architecture level, however, and covers as much ground as it possibly can - which, again, is usual in this space. For example, it allows for designs that even include multiple graphics processors working in tandem or just sections of graphics processors. The method applies to "a single processor desktop system, a multiprocessor workstation system, a server system," as well as within a system-on-Chip design (SoC) for mobile. These graphics processors or embodiments, as Intel calls them, are even described as accepting instructions from RISC, CISC, or VLIW commands. But Intel seems to be taking a page straight out of AMD's playbook, explaining that their MCM design's "hub" nature could include a single die aggregating the Memory and I/O controllers.
As the rate of semiconductor miniaturization slows (and continues to slow), companies have to find ways to scale performance while maintaining good yields. At the same time, they have to innovate on architecture, semiconductor manufacturing processes are getting more and more complex and exotic, with a higher number of required manufacturing steps, a higher number of masks, and finally integrating Extreme Ultraviolet Lithography (EUV) applications. We've been surfing the diminishing returns part of the equation for a while now: it's getting harder and harder to increase transistor density, and increasing die areas further would incur penalties on wafer yields. The only solution is to pair several smaller dies together: it's easier to have two functioning 400 mm squared dies than it is to have one fully working 800 mm one.
AMD, for one, has found great success with its MCM-based Ryzen CPUs ever since their first generation. The red company still delivers MCM-based GPUs, but their next-gen Navi 31 and Navi 32 may feature that technology. And we know Nvidia, too, is actively exploring MCM designs for its future graphics products, following its new Composable On Package GPU (COPA) design approach. The race has been on for a long time, even before AMD came out with Zen. The first company to deploy an MCM GPU design should have an advantage over its competitors, with higher yields facilitating higher profits - or lower market pricing. And with all three AMD, Intel, and Nvidia contracting the same TSMC manufacturing nodes in the foreseeable future, each slight advantage could have a potentially high market impact.
