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Two-Die Xeon? Leaked Sapphire Rapids Photo Appears to Show Chiplets

Sapphire Rapids
(Image credit: ServeTheHome Forums)

A member of ServeTheHome forums has published what he claims to be the first photos of Intel's Xeon Scalable 'Sapphire Rapids' processor. If the images are legitimate, they may shed some light on the design of the CPU and may indicate that it does not use a large monolithic die, but actually carries two dies. 

The photos depict an LGA processor with a metallic heat spreader carrying an 'Intel Confidential' mark, which indicates that this is a pre-production chip meant for testing and evaluation. Another engraving indicates a rather moderate 2.0 GHz frequency of the CPU which is something to be expected from an early sample. Also, since the processor is a pre-production sample, it has a four-character stepping: QTQ2. Since the device does not look like an existing Intel processor, it could well be a sample of Intel's upcoming Sapphire Rapids.

(Image credit: ServeTheHome Forums)

The front side of the alleged Sapphire Rapids processor reveals a rather intriguing detail. The heat spreader of the CPU has two bulges of about the same size. Intel's contemporary CPU heat spreaders do feature a number of convexities, but there is always one main 'bump' above the main die. Two bulges may indicate that Intel uses two processor dies for Sapphire Rapids instead of one monolithic die.

(Image credit: ServeTheHome Forums)

The back side of the CPU looks typical for Intel's latest server processors with its land grid array split into two domains. Meanwhile, there are two identical sets of capacitors in the middle of the package, which supports the theory that Intel's Sapphire Rapids is indeed a multi-chip-module (MCM) carrying two dies interconnected using one of Intel's latest technologies (e.g., EMIB). By contrast, Intel's monolithic dies have one set of capacitors on the back of their packaging. 

Using an MCM — or chiplet — design has a number of advantages when it comes to development and manufacturing. For obvious reasons, it is easier to design, emulate, and debug smaller chips. It is also easier to hit decent clocks and yield levels with smaller dies. On the other hand, large monolithic dies work more efficiently as internal interconnections are always faster than off-chip interconnects. 

As a rule, Intel does not comment on leaked information about its unreleased products, so do not expect the company to confirm or deny any facts about its Sapphire Rapids processor beyond what is has already been revealed.

(Image credit: Intel)

So far, Intel has publicly confirmed that its Sapphire Rapids processors will use the Golden Cove microarchitecture that supports Intel’s Advanced Matrix Extensions (AMX) as well as AVX512_BF16 and AVX512_VP2INTERSECT instructions that are particularly well suited for datacenter and supercomputer workloads. 

In addition to microarchitectural innovations, the new CPU will feature a DDR5 memory controller (enhanced with Intel’s Data Streaming Accelerator, DSA), the PCIe 5.0 bus with a 32 GT/s data transfer rate that is enriched with the CXL 1.1 protocol to optimize CPU-to-device (for accelerators) as well as CPU-to-memory (for memory expansion and storage devices) interconnects. Intel will produce Sapphire Rapids using its 10 nm Enhanced SuperFin technology.